1. Technical Field of the Invention
This invention relates generally to mixed signal integrated circuits and more particularly to multiple clocking modes of a system on a chip.
2. Description of Related Art
In general, a system on a chip (SOC) integrates multiple independent circuits, which are typically available as individual integrated circuits, on to a single integrated circuit. For example, an audio processing SOC combines a processing core (e.g., microprocessor and/or digital signal processor, instruction cache, and data cache), an audio codec (e.g., digitization of analog audio input signals and converting digitized audio signals into analog output signals), a clock circuit, a high speed serial interface (e.g., universal serial bus (USB) interface), and an external memory interface.
The clock circuit of an audio processing SOC typically includes an oscillation circuit and a phase locked loop (PLL). The oscillation circuit generates a reference oscillation from an off-chip crystal and the PLL generates one or more clock signals from the reference oscillation. Many applications of the audio processing SOC (e.g., music file playback, file transfers via the USB interface, etc.) require a highly accurate clock. Thus, the oscillation circuit and the PLL are designed to provide the highly accurate clock for these operating conditions, which comes with the cost of power consumption.
There are, however, many low power operating conditions of an audio processing SOC that do not require a highly accurate clock (e.g., USB suspend mode, fast start sleep modes, etc.). Since there is only one clock circuit on the audio processing SOC, the highly accurate clock is used and the corresponding power is consumed. In the low power operating modes, the power consumption of the system can be dominated by circuitry generating accurate clock frequencies, voltage references, etc.
Therefore, a need exists for a system on a chip (SOC) that includes a low power mode and a performance mode to reduce power consumption of the SOC.